Optimized Modulation Method for Common-Mode Voltage Reduction in H7 Inverter

The three-phase H7 inverter topology installs an additional power semiconductor switch to the positive or negative node of DC-link for reducing common-mode voltage (CMV) by disconnecting from DC source during zero-voltage vectors. conventional CMV reduction method uses modified discontinuous pulse width modulation (MDPWM) and generates a switching signal using logical operations. However, is unable eliminate entire dwell time It only has effect in limited area space vector where V7 zero applied. Therefore, this paper proposes optimized that can reduce proposed moves patterns adding offset guarantee one kind vector, V7, applied system. then turns off seventh disconnect source. As result, leakage current are attenuated vector. Simulation experimental results confirm validity method.